Simulating of charge build-up in irradiated MOS/SOI transistors
https://doi.org/10.29235/1561-2430-2019-55-4-498-504
Abstract
The charge build-up in the interface of silicon / buried oxide in n-channel MOS/SOI transistors depending on their geometric parameters and electrical modes during ionizing irradiation is calculated with the use of the software Silvaco. It is shown that the electrical mode is most “harsh”, when during irradiation the voltage of +5 V is applied to drain and source electrodes and 0 V is applied to substrate, gate and channel feeding. The amount of the built-up charge can be substantially reduced by applying a negative bias to the substrate and by decreasing the thickness of the buried oxide layer.
About the Authors
D. A. Ogorodnikov
SSPA “Scientific-Practical Materials Research Centre of NAS of Belarus”
Russian Federation
Russian Federation
Dmitriy A. Ogorodnikov – Junior Researcher.
19, P. Brovka Str., 220072, Minsk
S. B. Lastovskii
SSPA “Scientific-Practical Materials Research Centre of NAS of Belarus”
Russian Federation
Russian Federation
Stanislav B. Lastovskii – Ph. D. (Physics and Mathematics), Head of the Laboratory of Radiation Effects.
19, P. Brovka Str., 220072, Minsk
Yu. V. Bogatyrev
SSPA “Scientific-Practical Materials Research Centre of NAS of Belarus”
Russian Federation
Russian Federation
Yuriy V. Bogatyrev – Dr. Sc. (Engineering), Chief Researcher.
19, P. Brovka Str., 220072, Minsk
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