OPTIMIZATION OF MULTI-LEVEL REPRESENTATIONS OF LOGIC CIRCUITS TO REDUCE A VLSI CHIPAREA AND POWER CONSUMPTION

Abstract

The problem of optimization of multi-level representations of logic circuits taking into account two main characteristics of CMOS circuits (area and average dissipated power value) is developed. The results of a comparative study of two approaches to the construction of multi-level logic circuits design on the base of gates are presented. Such multi-level logic circuits are intended to cover a CMOS library with elements.